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| TX_RST | Write 1, then write 0 to this bit to reset decode state machine. |
| RX_RST | Write 1, then write 0 to this bit to reset encode state machine. |
| UART0_CE | Set this bit to link up HCI and UART0. |
| UART1_CE | Set this bit to link up HCI and UART1. |
| SEPER_EN | Set this bit to separate the data frame using a special char. |
| HEAD_EN | Set this bit to encode the data packet with a formatting header. |
| CRC_REC_EN | Set this bit to enable UHCI to receive the 16 bit CRC. |
| UART_IDLE_EOF_EN | If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state. |
| LEN_EOF_EN | If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received. |
| ENCODE_CRC_EN | Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. |
| CLK_EN | 1’b1: Force clock on for register. 1’b0: Support clock only when application writes registers. |
| UART_RX_BRK_EOF_EN | If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART. |